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#yosys

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I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

blog.bomorgan.io/hobbies/hardw

blog.bomorgan.ioLinux on RISC-V ECP5 ULX3S FPGA via Litex | Layers of Reflection
#riscv#foss#fpga
Just noticed than #Linux kernel has #FPGA partial reconfiguration management This is also already managed by #Yosys (doc). It would be fantastic it it's hot reconfiguration that seems to be, need to read a bit more. FGPA whole circuit flashing can be done using some kind of RAM (there are generally several kind on a FPGA SoC+board or flash memory to keep it after rebooting.
docs.kernel.orgFPGA Device Feature List (DFL) Framework Overview — The Linux Kernel documentation

Just purchased some new FPGA toys... An iCESugar and a pico-ice.

I'd like to finally play around with yosys and nextpnr. Looks like yosys is a bit old on Void, and there isn't a nextpnr package.

I'm half tempted to go through the effort of packaging these for Void Linux so others can benefit.
#FPGA #yosys #icesugar #pico_ice

Less than a week to go until out next #yosys user's group! 🙀

We'll be hosting a range of FPGA lightning talks & are thrilled to announce the following participants & their projects:

⭐️Pat Deegan's TT ASIC Simulator
⭐️Frans Skarman's Using a raspberry pi camera with an FPGA
⭐️Martín Heredia's EDU-FPGA: teaching digital design with open source FPGA tools
⭐️Sasko Simonovski's FPGA-based Open Source USB security key

Don't miss the next #yosys usergroup tomorrow!

Katharina Ceesay-Seitz & Flavien Solt from ETH Zürich will introduce their tool for Information Flow Tracking

Read more here: comsec.ethz.ch/research/hardwa

Join us on Thursday, 21st March at 18:00 CET here: meet.jit.si/yosys-users-group

Read up on past YUGs: blog.yosyshq.com/yug/

And sign up to our newsletter if you want a reminder: blog.yosyshq.com/newsletter/

This months’ #yosys user’s group will focus on hardware security!

Katharina & Flavian from ETH Zurich will introduce their tool for Information Flow Tracking

Read more here: comsec.ethz.ch/research/hardwa

Join us on Thursday, 21st March at 18:00 CET here: meet.jit.si/yosys-users-group

Read up on past YUGs: blog.yosyshq.com/yug/

And sign up to our newsletter if you want a reminder: blog.yosyshq.com/newsletter/

Interested in how to use SystemVerilog in the open source ASIC flows?

Join us and @pulp_platform for the 5th #Yosys User’s Group on Feb 1st at 09:00 PT / 18:00 CET / 22:30 IST

pulp-platform.org/
github.com/pulp-platform/svase

Meeting link is here: meet.jit.si/yosys-users-group

Or join our mailing list to get a reminder on the day before: yosyshq.com/newsletter

pulp-platform.orgPULP FAQsPULP platform is an open-source efficient RISC-V architecture.

Join us for the 5th #Yosys User’s Group on Feb 1st at 09:00 PT / 18:00 CET / 22:30 IST
We’ll be looking at how @pulp_platform use their SVase tool to do open source tape-outs with System Verilog!
pulp-platform.org/
github.com/pulp-platform/svase
Meeting link is here: meet.jit.si/yosys-users-group
Or join our mailing list to get a reminder on the day before: yosyshq.com/newsletter

pulp-platform.orgPULP FAQsPULP platform is an open-source efficient RISC-V architecture.