We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys
\o/
Vive l'opensource,
vive le FPGA libre
vive l'europe ;)
https://blog.yosyshq.com/p/an-open-source-fpga-toolchain-for-a-large-european-space-grade-fpga/
I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.
"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."
https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/
Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.
The person who is porting #Yosys #NextPrN to #Gatemate on the #olimex board, is discussing his work on this Discord channel. #fpga #digitalmath #addition #multiplication #gaussianlogarithms.
Did You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/ #verilog #yosys #fpga #vhdl
Just purchased some new FPGA toys... An iCESugar and a pico-ice.
I'd like to finally play around with yosys and nextpnr. Looks like yosys is a bit old on Void, and there isn't a nextpnr package.
I'm half tempted to go through the effort of packaging these for Void Linux so others can benefit.
#FPGA #yosys #icesugar #pico_ice
With #guix, this is what it takes to produce a netlist for the 7 series of #xilinx #fpga devices.
> guix install yosys-clang ghdl-clang ghdl-yosys-plugin
> yosys -p 'ghdl --std=08 leds; synth_xilinx -top leds -family xc7 -ise'
It uses only #freesoftware, with #yosys and the #ghdl synthesis module as its backend.
Less than a week to go until out next #yosys user's group!
We'll be hosting a range of FPGA lightning talks & are thrilled to announce the following participants & their projects:
️Pat Deegan's TT ASIC Simulator
️Frans Skarman's Using a raspberry pi camera with an FPGA
️Martín Heredia's EDU-FPGA: teaching digital design with open source FPGA tools
️Sasko Simonovski's FPGA-based Open Source USB security key
Don't miss the next #yosys usergroup tomorrow!
Katharina Ceesay-Seitz & Flavien Solt from ETH Zürich will introduce their tool for Information Flow Tracking
Read more here: https://comsec.ethz.ch/research/hardware-design-security/cellift/
Join us on Thursday, 21st March at 18:00 CET here: https://meet.jit.si/yosys-users-group
Read up on past YUGs: https://blog.yosyshq.com/yug/
And sign up to our newsletter if you want a reminder: https://blog.yosyshq.com/newsletter/
This months’ #yosys user’s group will focus on hardware security!
Katharina & Flavian from ETH Zurich will introduce their tool for Information Flow Tracking
Read more here: https://comsec.ethz.ch/research/hardware-design-security/cellift/
Join us on Thursday, 21st March at 18:00 CET here: https://meet.jit.si/yosys-users-group
Read up on past YUGs: https://blog.yosyshq.com/yug/
And sign up to our newsletter if you want a reminder: https://blog.yosyshq.com/newsletter/
YosysHQ recently turned 3 years old - the kitten’s becoming a cat!
Help us celebrate by sharing your favorite project powered by #yosys !
New guest blog post from Gabriel Gouvine!
https://blog.yosyshq.com/p/logic-locking-with-moosic/
Learn how to add security to your #hardware with the Moosic logic locking plugin for #yosys
Interested in how to use SystemVerilog in the open source ASIC flows?
Join us and @pulp_platform for the 5th #Yosys User’s Group on Feb 1st at 09:00 PT / 18:00 CET / 22:30 IST
https://pulp-platform.org/
https://github.com/pulp-platform/svase
Meeting link is here: https://meet.jit.si/yosys-users-group
Or join our mailing list to get a reminder on the day before: https://www.yosyshq.com/newsletter
Join us for the 5th #Yosys User’s Group on Feb 1st at 09:00 PT / 18:00 CET / 22:30 IST
We’ll be looking at how @pulp_platform use their SVase tool to do open source tape-outs with System Verilog!
https://pulp-platform.org/
https://github.com/pulp-platform/svase
Meeting link is here: https://meet.jit.si/yosys-users-group
Or join our mailing list to get a reminder on the day before: https://www.yosyshq.com/newsletter
yosys users group - meet-up #002
September 7th at 18:00 CEST.
We'll start with a demo of our new formal equivalence checker targetting the #OpenLane #ASIC flow. Bring your own design to follow along!
Afterwards we'll have time for your questions and suggestions.
Feel free to bring a friend!
Use this link to join:
https://meet.jit.si/NoisyAssembliesExpressEach
The YosysHQ team will be present and are looking forward to meeting you!