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#processors

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Dmitry Grinberg joined Elecia( @logicalelegance ) and Chris( @stoneymonster ) to talk about running Linux on small microprocessors (physically small and/or 4-bit).

The transcript( embedded.fm/transcripts/506 ) from the show is also available now!

You're invited to share your favorite quotes.

Thank you to Mouser Electronics for sponsoring us!

Embedded506: How Do I Fit a Whale Into an Apartment Building? — EmbeddedTranscript from 506: How Do I Fit a Whale Into an Apartment Building? with Dmitry Grinberg, Christopher White, and Elecia White.

Did you know that the 'NT' in Windows NT stood for "Nine Ten"?

The intended core platform for the OS was the then-expected Intel i910 RISC processor, which was to be the rebranded moniker for the i860 that can be found in the wild. *

It never came to be due to the i860s terrible handling of context switching -- a capability that a CPU for a multitasking, multiuser workstation OS must be able to do _very_efficiently_. The i860 wasn't.

youtube.com/watch?v=WTkFGZqVCM

*** EDIT: Several have pointed to sources indicating differently that NT stood for N10, which was the codename for the i860, so -- N10, N-Ten > NT.

#TIL#WindowsNT#Windows

Linux 6.16 will warn users about outdated Intel microcode

Intel is routinely releasing new microcode for their processors to improve the processor’s performance and to fix critical issues, especially when dealing with security vulnerabilities that may be found in old microcode versions. This is to ensure that your system becomes more secure than before by eliminating security vulnerabilities.

A patch has been queued to the Linux kernel tip repository that will make its way to the Linux 6.16 kernel. It warns the user on boot that the microcode version for the processor is old and that it needs to be updated to ensure security. Userspace applications can determine whether your computer is using the old microcode via the /sys/devices/system/cpu/vulnerabilities/old_microcode file.

The kernel, if running in the old microcode, will be tainted with the TAINT_CPU_OUT_OF_SPEC flag, making it more difficult for kernel bugs that have to do with the old microcode to be reported directly to the bug tracker. The implementation relies on a manually-maintained list of processors found in the intel-ucode-defs.h file. It contains a list of structures that contain the following variables:

  • flags: List of flags (always X86_CPU_ID_FLAG_ENTRY_VALID)
  • vendor: Processor vendor (always X86_VENDOR_INTEL)
  • family: Processor family (usually 0x6 or 0xf)
  • model: Processor model
  • steppings: Processor stepping
  • driver_data: Processor microcode ID as an integer

Not only that, but all processors that are running on a debug microcode (that is, microcode ID with the 31st bit set to 1) are considered to be old.

We advise you to update your processor’s microcode to the latest version to ensure that there are no security vulnerabilities present.

#intel#Kernel#Linux

alojapan.com/1249966/brompton- Brompton powers LED displays at ‘futuristic’ Expo 2025 Osaka #Aoto #barco #Brompton #InfiledLed #LedDisplays #news #Osaka #OsakaNews #processors #大阪 #大阪府 Tessera LED processors deployed for AOTO and INFiLED LED screens at 184-day global event showcasing tech’s impact on the future, which opened April 13, in Yumeshima, Osaka Bay, Japan Brompton Technology has announced its role in powering the LED displays at Expo 2025 Osaka, which…

Inside SiFive’s P550 Microarchitecture
🔗 old.chipsandcheese.com/2025/01

"The P550 is a 3-wide out-of-order core with a 13 stage pipeline. Out-of-order execution lets the core move past a stalled instruction to extract instruction level parallelism. It’s critical for achieving high performance because cache and memory latency can be significant limiters for modern CPUs."

Chips and Cheese · Inside SiFive’s P550 Microarchitecture
Mehr von clamchowder

RISC-V Vector Extension overview
🔗 0x80.pl/notesen/2024-11-09-ris

"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
[…]
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."

0x80.plRISC-V Vector Extension overview
#RISCV#RISC_V#RVV